Pcram structure

ABSTRACT

A memory device includes the following items. A substrate. A bottom electrode disposed over the substrate. An insulating layer disposed over the bottom electrode, the insulating layer having a through hole defined in the insulating layer. A heater disposed in the through hole. A phase change material layer disposed over the heater. A selector layer disposed over the phase change material layer. An intermediate layer disposed over the through hole. Also, a metal layer disposed over the selector layer. The metal layer is wider than the phase change material layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. Provisional Patent Application62/694,855 filed Jul. 6, 2018, the entire disclosure of which isincorporated herein by reference.

TECHNICAL FIELD

The disclosure relates to a device of a phase change random accessmemory (PCRAM) and method of manufacturing the same. In particular, thepresent application discloses, in some embodiments of the presentdisclosure, a phase change random access memory (PCRAM) with full TaNbottom electrode (BE) structure and method of manufacturing the same.

BACKGROUND

Phase change random access memory (PCRAM) is a non-volatile memorydevice making use of different resistive phases and heat induced phasetransition between the phases of phase change materials includingchalcogenide and resistive materials. A PCRAM is composed of many cellseach of which functions independently. A PCRAM cell mainly includes aheater and a resistor which is a data storage element made mainly of areversible phase change material to provide at least two dramaticallydifferent resistivities for logical “O” state and “1” state.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure is best understood from the following detaileddescription when read with the accompanying figures. It is emphasizedthat, in accordance with the standard practice in the industry, variousfeatures are not drawn to scale and are used for illustration purposesonly. In fact, the dimensions of the various features may be arbitrarilyincreased or reduced for clarity of discussion.

FIG. 1(a) shows a top view of a PCRAM according to an embodiment of thepresent disclosure, and FIG. 1(b) shows a cross-sectional view of thePCRAM along a cut line I-I′ of FIG. 1(a).

FIG. 2(a) shows a top view of a PCRAM according to another embodiment ofthe present disclosure, and FIG. 2(b) shows a cross-sectional view ofthe PCRAM along a cut line I-I′ of FIG. 2(a).

FIG. 3(a) shows a top view of a PCRAM according to another embodiment ofthe present disclosure, and FIG. 3(b) shows a cross-sectional view ofthe PCRAM along a cut line I-I′ of FIG. 3(a).

FIG. 4 shows a cross-sectional view of a PCRAM according to anotherembodiment of the present disclosure.

FIG. 5(a) shows a cross-sectional view of a PCRAM according to anotherembodiment of the present disclosure, and FIG. 5(b) shows across-sectional view of an alternative embodiment of the PCRAM of FIG.5(a).

FIG. 6(a) shows a cross-sectional view of a PCRAM according to anotherembodiment of the present disclosure, and FIGS. 6(b) and 6(c) showcross-sectional views of alternative embodiments of the PCRAM of FIG.6(a).

FIGS. 7(a), 7(b), 7(c), 7(d), 7(e), 7(f) and 7(g) show sequentialmanufacturing operations for forming a PCRAM according to embodiments ofthe present disclosure.

FIGS. 8(a), 8(b), 8(c), 8(d), 8(e), 8(f), 8(g), 8(h), and 8(i) showsequential manufacturing operations for forming a PCRAM according toembodiments of the present disclosure.

FIGS. 9(a), 9(b), 9(c), 9(d), 9(e), 9(f), 9(g), and 9(h) show sequentialmanufacturing operations for forming a PCRAM according to embodiments ofthe present disclosure.

FIGS. 10(a), 10(b), 10(c), 10(d), 10(e), 10(f), and 10(g), showsequential manufacturing operations for forming a PCRAM according toembodiments of the present disclosure.

FIG. 11 shows a method of forming a PCRAM according to embodiments ofthe present disclosure.

FIGS. 12(a), 12(b), 12(c), 12(d), 12(e), and 12(f) show sequentialmanufacturing operations for forming a heater in a through holeaccording to embodiments of the present disclosure.

FIGS. 13(a), 13(b), 13(c), and 13(d) show sequential manufacturingoperations for depositing a two-dimensional layer on top of the heaterwhen forming a PCRAM according to embodiments of the present disclosure.

FIGS. 14(a) and 14(c) show a structure of top and bottom electrodes thatare coupled to a heater. FIG. 14(b) shows an elemental analysis results.

DETAILED DESCRIPTION

It is to be understood that the following disclosure provides manydifferent embodiments, or examples, for implementing different featuresof the invention. Specific embodiments or examples of components andarrangements are described below to simplify the present disclosure.These are, of course, merely examples and are not intended to belimiting. For example, dimensions of elements are not limited to thedisclosed range or values, but may depend upon process conditions and/ordesired properties of the device. Moreover, the formation of a firstfeature over or on a second feature in the description that follows mayinclude embodiments in which the first and second features are formed indirect contact, and may also include embodiments in which additionalfeatures may be formed interposing the first and second features, suchthat the first and second features may not be in direct contact. Variousfeatures may be arbitrarily drawn in different scales for simplicity andclarity.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly. In addition, the term“being made of” may mean either “comprising” or “consisting of.” In thepresent disclosure, a phrase “one of A, B and C” means “A, B and/or C”(A, B, C, A and B, A and C, B and C, or A, B and C), and does not meanone element from A, one element from B and one element from C, unlessotherwise described.

Generally, to read a state (data) from the PCRAM cell, a sufficientlysmall current is applied to the phase change material without triggeringthe heater to generate heat. In this way, the resistivity of the phasechange material can be measured and the states representing theresistivities, i.e. a “0” state for high resistivity or a “1” state forlow resistivity can be read. To write a state (data) in the PCRAM cell,for example, to write a “1” state representing a low resistivity phaseof the phase change material, a medium electric current is applied tothe heater which generates heat for annealing the phase change materialat a temperature above the crystallization temperature but below themelting temperature of the phase change material for a time period toachieve a crystalline phase. To write a “0” state representing a highresistivity phase of the phase change material, a very large electriccurrent is applied to the heater to generate heat to melt the phasechange material at a temperature higher than the melting temperature ofthe phase change material; and the electric current is abruptly cut offto lower the temperature to below the crystallization temperature of thephase change material to quench and stabilize the amorphous structure ofphase change material so as to achieve the high-resistance logical “0”state. The very large electric current can thus be in a pulse form. Inthe present disclosure, a PCRAM having improved cell structures areexplained.

FIG. 1(a) shows a top view of a PCRAM having a substrate 100, a bottomelectrode 120 formed over the substrate 100 where the bottom electrodemay be a bit line, a phase change material layer 130 formed over thebottom electrode 120, and a metal layer 110 formed over the phase changematerial layer 130. In this embodiment, the size of the phase changematerial layer 130 is the same as the overlapped area between the bottomelectrode 120 and the metal layer 110 which functions as a topelectrode.

In some embodiments, the substrate 100 comprises a single crystallinesemiconductor material such as, but not limited to Si, Ge, SiGe, GaAs,InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. In certainembodiments, the substrate 100 is made of crystalline Si. In someembodiments, the metal layer 110 and the bottom electrode 120 are formedof the same material or different materials, including one or morelayers of conductive material, such as polysilicon, aluminum, copper,titanium, tantalum, tungsten, cobalt, molybdenum, carbon, tantalumnitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN,TaC, TaSiN, metal alloys such as aluminum copper alloy, other suitablematerials, and/or combinations thereof. Each of the metal layer 110 andthe bottom electrode 120 has a thickness in a range from about 20 toabout 2,000 nm in some embodiments. In some embodiments, the substrate100 is a semiconductor-on-insulator substrate fabricated usingseparation by implantation of oxygen (SIMOX), wafer bonding, and/orother suitable methods, such as a silicon-on-insulator (SOI) substrate,a silicon germanium-on-insulator (SGOI) substrate, or agermanium-on-insulator (GOI) substrate. In some embodiments, thesubstrate 100 includes transistors such as MOSFET planar transistors,FinFETs, and Gate All Around (GAA) transistors, metal lines such aspoly-lines and interconnect metal lines, and the transistors control theoperations of the PCRAM. In some embodiments, the bottom electrode 120is a metal line connected with the transistors included by the substrate100.

FIG. 1(b) shows a cross-sectional view of the PCRAM having insulatinglayer 150 which includes a through hole h. In the through hole h, aheater 140 is formed. In some embodiments, the heater 140 is formed ofthin film material of TiN, TaN, or TiAlN that has a thickness in a rangefrom about 5 to about 15 nm to provide Joule heating to the phase changematerial layer 130. Also, the heater 140 may function as a heat sinkduring quenching (during abrupt cutoff of the current applied to theheater 140 to ‘freeze’ the amorphous phase). The heater 140 fills thethrough hole h provided in the insulating layer 150 which prevents heattransfer between PCRAM cells so as to avoid thermal disturbance whichmay disable state retention or interrupt the read/write process.

In some embodiments, the insulating layer 150 is composed of, but notlimited to, silicon oxide (SiO₂), silicon nitride (Si₃N₄), siliconoxynitride (SiON), SiOCN, SiCN, Al₂O₃, fluorine-doped silicate glass(FSG), a low-k dielectric material, or various other suitable dielectricmaterials used in manufacturing semiconductor devices. The insulatinglayer 150 disposed over the patterned bottom electrode 120 is anelectrical and thermal insulator, and has a thickness in a range fromabout 5 to about 350 nm in some embodiments.

The phase change material layer 130 receives the heat generated by theheater 140, and a region (called “active region”) close to the interfacebetween the phase change material layer 130 and the heater 140 undergoesa phase transition from crystalline phase to amorphous phase or viceversa, depending on the amount and duration of heat generated when anelectric current is applied to the heater 140. In the embodiment in FIG.1(b), the active region has a mushroom-shape (FIG. 1(b)), while theregion outside the active region does not undergo phase transition andmay function as heat insulating layer to preserve the heat inside themushroom-shaped active region. The smaller the active region, the lessan amount of heat and thus less current is required for writing to thePCRAM cell. In some embodiments, the material of the phase changematerial layer 130 is a binary system of Ga—Sb, In—Sb, In—Se, Sb—Te,Ge—Te, and Ge—Sb; a ternary system, of Ge—Sb—Te, In—Sb—Te, Ga—Se—Te,Sn—Sb—Te, In—Sb—Ge, and Ga—Sb—Te; or a quaternary system of Ag—In—Sb—Te,Ge—Sn—Sb—Te, Ge—Sb—Se—Te, Te—Ge—Sb—S, Ge—Sb—Te—O, and Ge—Sb—Te—N. Insome embodiments, the material for the phase change material layer 130is a chalcogenide alloy containing one or more elements from Group VI ofthe periodic table, such as a GST, a Ge—Sb—Te alloy (e.g. Ge₂Sb₂Te₅)having a thickness of 5 to 100 nm. The phase change material layer 130may include other phase change resistive materials, such as metal oxidesincluding tungsten oxide, nickel oxide, copper oxide, etc. The phasetransition between the crystalline phase and the amorphous phase of thephase change material is related to the interplay between the long rangeorder and the short range order of the structure of the phase changematerial. For example, collapse of the long range order generates theamorphous phase. The long range order in the crystalline phasefacilitates electrical conduction, while the amorphous phase impedeselectrical conduction and results in high electrical resistance. To tunethe properties of the phase change material layer 130 for differentneeds, the material of the phase change material layer 130 may be dopedwith various elements, e.g., B, Al, As, Ga, or P, at different amountsto adjust the proportion of the short range order and the long rangeorder inside the bonding structure of the material. The doped elementmay be any element used for semiconductor doping through the use of, forexample, ion implantation.

A selector layer 160 is formed over the phase change material layer 130,and a metal layer 110 and an intermediate layer 170 are formed over theselector layer 160. In a phase change memory array, for example, across-point array with hundreds or more memory cells, many problemsdisturbing the proper operation of a memory cell may occur. The problemsmay be electrical in nature, such as leakage current, parasiticcapacitance, etc. The problems may also be thermal in nature, such as athermal disturbance between memory cells. To solve the above problems, aswitching device is used to reduce or avoid leakage current from anoperating memory cell or from other memory cells passing along theresistive network. By using a switching device, the heaters of othermemory cells would not be accidentally turned on by a leakage current,thereby wiping off the recorded states in the memory cells. A switchingdevice functioning like a diode device or a transistor device is used sothat only the intended PCRAM cells are selected for read/write whileother PCRAM cells are not turned on, and to reduce or prevent leakagecurrent originating from the selected PCRAM cells. To provide accurateread/write operations, a selector layer having high on-stateconductivity and infinite off-state resistance is desired to be formedover the phase change material layer 130 to reduce the power dissipationin the resistive network of the PCRAM, leakage current and cross-talkdisturbance, while making sure only the selected PCRAM cells areundergoing read/write operation. In this way, a reliable PCRAM can beformed. Considering the size of the switching device, a diode type (suchas a p-n junction diode, a Schottky diode, a metal-insulator transitionMIT, and an ovonic threshold switch OTS) device may have a smaller sizethan a transistor type (such as a MOSFET,metal-oxide-semiconductor-field-effect-transistor) device. The selectorlayer 160 may function as a diode type device with a diode junctionformed within the selector layer 160. In FIG. 1(b), the selector layeris formed over and patterned with the phase change material layer 130formed of the aforementioned materials to have the same size, greatlyreducing the space within the PCRAM for the selector device which isconsidered a limiting factor for the shrinking trend of memory devices.In some embodiments, the selector layer 160 provides a current-voltagenon-linearity to the PCRAM, and this reduces leakage current. Theselector layer 160 has a single-layer or multi-layered structure, insome embodiments. In some embodiments, the selector layer 160 is made ofa material including SiO_(x), TiO_(x), AlO_(x), WO_(x),Ti_(x)N_(y)O_(z), HfO_(x), TaO_(x), NbO_(x), or the like, or suitablecombinations thereof, where x, y and z are non-stoichiometric values. Insome embodiments, the selector layer 160 is a solid-electrolyte materialcontaining one or more of Ge, Sb, S, Te or a chalcogenide such as N, P,S, Si, and/or Te doped chalcogenide such as N, P, S, Si, and/or Te dopedAsGeSe, i.e. AsGeSe(N, P, S, Si, Te), and N, P, S, Si, and/or Te dopedAsGeSeSi, i.e. AsGeSeSi(N, P, S, Si, Te). The thickness of the selectorlayer 160 is in a range from about 0.5 nm to about 50 nm. In someembodiments, the selector layer 160 is formed by chemical vapordeposition (CVD), pulsed laser deposition (PLD), sputtering, atomiclayer deposition (ALD) or any other thin film deposition method.

The intermediate layer 170 is formed over the through hole h and betweenthe selector layer 160 and the metal layer 110, in some embodiments ofthe present disclosure. The intermediate layer 170 may be formed ofcarbon, titanium, titanium nitride, tungsten, and titanium-tungsten witha thickness of about 1 to 50 nm and functions to prevent materialdiffusion into and contamination of the phase change material layer 130.In some embodiments, the intermediate layer 170 is formed by any vapordeposition method such as CVD, PLD, sputtering, ALD, or any other thinfilm deposition method. In some embodiments, the intermediate layer 170reduces the incorporation of species from the metal layer 110 into theselector layer 160 and the phase change material layer 130. In someembodiments of the present disclosure, the in-plane size of theintermediate layer 170 is greater than the horizontal cross-sectionalsize of the through-hole h.

FIG. 2(a) shows a top view of a PCRAM according to another embodiment ofthe present disclosure. Materials, configurations, dimensions, and/orprocesses explained with respect to FIGS. 1(a) and 1(b) may be employedin the following embodiments, and the detailed explanation thereof maybe omitted.

The PCRAM has a substrate 100, a bottom electrode 120 formed over thesubstrate 100 where the bottom electrode may be a bit line, a phasechange material layer 130 formed over the bottom electrode 120, and ametal layer 110 formed over the phase change material layer 130. In thisembodiment, the size of the phase change material layer 130 is smallerthan the overlapped area between the bottom electrode 120 and the metallayer 110 which functions as a top electrode. That is, the size of thephase change material layer 130 in the embodiment of FIG. 2(a) issmaller than the size of the phase change material layer 130 in theembodiment of FIG. 1(a). The smaller phase change material layer 130provides a benefit of reduced operating electric current required to besupplied to the heater to heat the phase change material layer 130 forwriting, and thus significantly reducing the overall power consumptionof a memory having over a thousand phase change material layers 130.

FIG. 2(b) shows a cross-sectional view of the PCRAM according to theembodiment shown in FIG. 2(a). The PCRAM has an insulating layer 150which includes a through hole h. In the through hole h, a heater 140 isformed. In some embodiments, the heater 140 is formed of thin filmmaterial of TiN, TaN, or TiAlN that has a thickness in a range fromabout 5 to about 15 nm to provide Joule heating to the phase changematerial layer 130. Also, the heater 140 may function as a heat sinkduring quenching (during abrupt cutoff of the current applied to theheater 140 to ‘freeze’ the amorphous phase). The heater 140 fills thethrough hole h provided in the insulating layer 150 which prevents heattransfer between PCRAM cells so as to avoid thermal disturbance whichmay disable state retention or interrupt the read/write process. Thephase change material layer 130 is formed in the through hole h and maycontact the heater 140. In this way, the active region in the phasechange material layer 130 undergoing phase transition during writing ofthe memory cell is different from that in FIG. 1(b) which has a mushroomshape. A selector layer 160 is formed over the phase change materiallayer 130 and has a size (width of about 25 nm to about 100 nm) greaterthan the phase change material layer 130 in the through hole having awidth of about 10 nm. A metal layer 110 is formed over the selectorlayer 160 and functions as a top electrode for the read/write operationof the PCRAM cell.

The phase change material layer 130 receives the heat generated by theheater 140, and a region (called “active region”) close to the interfacebetween the phase change material layer 130 and the heater 140 undergoesa phase transition from crystalline phase to amorphous phase or viceversa, depending on the amount and duration of heat generated when anelectric current is applied to the heater 140. In the embodiment in FIG.2(b), the active region has an oval shape (FIG. 2(b)), while the regionoutside the active region does not undergo phase transition and mayfunction as heat insulating layer to preserve the heat inside the activeregion. The smaller the active region, the less an amount of heat andthus less current is required for writing to the PCRAM cell.

A selector layer 160 is formed over the phase change material layer 130,and a metal layer 110 is formed over the selector layer 160. In FIG.2(b), the selector layer 160 is formed over the phase change materiallayer 130 formed of the aforementioned materials to have a greater sizethan the phase change material layer 130, greatly enhancing thecontrollability and selectability of the phase change material layer130. In some embodiments, the selector layer 160 provides acurrent-voltage non-linearity to the PCRAM, and this reduces leakagecurrent. The selector layer 160 has the above structures. In someembodiments, the selector layer 160 is made of the above mentionedmaterials in the above description of FIG. 1(b). The thickness of theselector layer 160 is in a range from about 0.5 nm to about 50 nm. Insome embodiments, the selector layer 160 is formed by CVD, PLD,sputtering, ALD, or any other thin film deposition method.

The intermediate layer 170 is formed over the through hole h and betweenthe selector layer 160 and the metal layer 110, in some embodiments,similar to FIGS. 1(a) and 1(b).

FIG. 3(a) shows a top view of a PCRAM according to another embodiment ofthe present disclosure. Materials, configurations, dimensions, and/orprocesses explained with respect to FIGS. 1(a) to 2(b) may be employedin the following embodiments, and the detailed explanation thereof maybe omitted.

The PCRAM has a substrate 100, a bottom electrode 120 formed over thesubstrate 100 where the bottom electrode may be a bit line, a phasechange material layer 130 formed over the bottom electrode 120, and ametal layer 110 formed over the phase change material layer 130. In thisembodiment, the size of the phase change material layer 130 is smallerthan the overlapped area between the bottom electrode 120 and the metallayer 110 which functions as a top electrode. That is, the size of thephase change material layer 130 in the embodiment of FIG. 3(a) issmaller than the size of the phase change material layer 130 in theembodiment of FIG. 1(a). The smaller phase change material layer 130provides a benefit of reduced operating electric current required to besupplied to the heater to heat the phase change material layer 130 forwriting, and thus significantly reducing the overall power consumptionof a memory having over a thousand phase change material layers 130.

Although the top view is the same as that shown in FIG. 2(a), the devicestructure is different from FIG. 2(b). The PCRAM has an insulating layer150 which includes a through hole h. In the through hole h, a heater 140is formed. In some embodiments, the heater 140 is formed of thin filmmaterial of TiN, TaN, or TiAlN that has a thickness in a range fromabout 5 to about 15 nm to provide Joule heating to the phase changematerial layer 130. Also, the heater 140 may function as a heat sinkduring quenching (during abrupt cutoff of the current applied to theheater 140 to ‘freeze’ the amorphous phase). The heater 140 fills thethrough hole h provided in the insulating layer 150 which prevents heattransfer between PCRAM cells so as to avoid thermal disturbance whichmay disable state retention or interrupt the read/write process.

Also, as shown in the cross-sectional view in FIG. 3(b), the selectorlayer 160 is formed in the through hole h, greatly reducing the spaceoccupied by the selector device in the PCRAM cell. A metal layer 110 isformed over the selector layer 160 and functions as a top electrode forthe read/write operation of the PCRAM cell.

A selector layer 160 is formed over the phase change material layer 130,and a metal layer 110 is formed over the selector layer 160. In FIG.3(b), the selector layer is formed over and patterned with the phasechange material layer 130 formed of the aforementioned materials to havethe same size, greatly reducing the space within the PCRAM for theselector device which is considered a limiting factor for the shrinkingtrend of memory devices. In some embodiments, the selector layer 160provides a current-voltage non-linearity to the PCRAM, and this reducesleakage current. The selector layer 160 has the above structures. Insome embodiments, the selector layer 160 is made of the above mentionedmaterials in the above description of FIG. 1(b). The thickness of theselector layer 160 is in a range from about 0.5 nm to about 50 nm. Insome embodiments, the selector layer 160 is formed by CVD, PLD,sputtering, ALD, or any other thin film deposition method.

The intermediate layer 170 is formed between the selector layer 160 andthe metal layer 110, in some embodiments, similar to FIGS. (lb) and2(b).

A stacked PCRAM structure greatly increases the memory cell density andcapacity in some embodiments. FIGS. 4, 5(a), 5(b), and 6(a) to 6(c) showvarious embodiments having stacked three-dimensional (3D) structures.Materials, configurations, dimensions, and/or processes explained withrespect to FIGS. 1(a)-3(b) may be employed in the following embodiments,and the detailed explanation thereof may be omitted.

FIG. 4 shows a cross-sectional view of a stacked structure of a PCRAMincluding a bottom electrode 120 and top electrode 120′. Between thebottom electrode 120 and the top electrode 120′, insulating layers 150,150′ and 150″ are disposed. In some embodiments, the insulating layers150, 150′ and 150″ are formed of the same materials described above withregard to FIGS. 1(b), 2(b), and 3(b). The insulating layers 150, 150′,and 150″ disposed over the patterned bottom electrode 120 are electricaland thermal insulators, and each has a thickness in a range from about 5to about 350 nm in some embodiments. Also, in some embodiments, theinsulating layers 150′ and 150″ are formed as one layer by a singleoperation. The insulating layers 150, 150′ and 150″, with the top andbottom electrodes 120′ and 120, enclose a first heater 140 and a secondheater 140′, a first phase change material layer 130 and a second phasechange material layer 130′, a first selector layer 160 and a secondselector layer 160′, and a metal layer 110. The first and second heaters140 and 140′ are formed in a first through hole h and a second throughhole h′, respectively, while the other components occupy a greater spaceprovided in the insulating layer 150′. Each of the through holes h andh′ is formed between the first or second phase change material layer 130or 130′ and the top or bottom electrode 120 or 120′.

The intermediate layer 170 is formed over the through hole h and betweenthe selector layer 160 and the metal layer 110, in some embodiments ofthe present disclosure.

The embodiment shown in FIG. 4 has a symmetrical structure with thedevice components arranged with respect to the metal layer 110 and theintermediate layer 170. Each of the first and second phase changematerial layers 130 and 130′ can be operated independently, and in thisdevice structure, instead of four electrodes, only three electrodes,e.g. the bottom electrode 120, the top electrode 120′ and the metallayer 110, are required to operate the two phase change material layers130 and 130′. In this way, an electrode is eliminated and the devicethickness is reduced, and the device structure and processing aresimplified with reduced manufacturing cost and simplified manufacturingoperations. Also, since the entire device is enclosed by the insulatinglayers 150, 150′, and 150″, the thermal disturbance and electricaldisturbance, such as leakage current, are beneficially reduced. Also,because of the higher thermal insulation property, the electric currentfor writing the memory cell is reduced in some embodiments as thetemperature of phase transition within this highly insulating system canbe achieved by a lower electric current. Depending on the choice ofheater material of the heaters 140 and 140′, the efficiency of theentire stacked device can be greatly increased in some embodiments.

The embodiment in FIG. 4 stacks two of the devices of the embodiment ofFIG. 1(a) along a vertical direction to form a stacked device; however,other possibilities are included in this disclosure, as would beappreciated by one of ordinary skill in the art. For example, in someembodiments, the lower half of the device is formed by the structure ofthe embodiment in FIG. 1(a) and the upper half of the device is, forexample, formed by the structure of the embodiment in FIG. 2(b), forminga non-symmetrical 3D structure of a PCRAM.

FIG. 5(a) shows a stacked device having a stacked structure symmetricalwith respect to the metal layer 110. The stacked device includes phasechange material layers 130 and 130′ on opposing sides of the metal layer110 formed in the through holes h and h′ that contact the heaters 140and 140′ in some embodiments. In this way, the active regions undergoingphase transition during writing of the memory cell is different fromthat in FIGS. 1(a) and 4 which have a mushroom shape. The smaller phasechange material layers 130 and 130′ significantly lower the operatingelectric current and reduce the overall power consumption of a memoryhaving over a thousand phase change material layers in some embodiments.First selector layer 160 and second selector layer 160′ are formed overthe respective first phase change material layer 130 and second phasechange material layer 130′. The first selector layer 160 and secondselector layer 160′ are larger than the respective first and secondphase change material layers 130 and 130′. The second selector layer160′ is formed of the same material as the selector layer 160, in someembodiments. In some embodiments, the second selector layer 160′ isformed of a material in the above group of materials used to make theselector layer 160, which is different from the selector layer 160. Insome embodiments, the selector layer 160′ has the same layered-structureas the selector layer 160. In some embodiments, the selector layer 160′has a different layered-structure than the selector layer 160, forexample, but not limited to, the selector layer 160′ has a single-layerstructure while the selector layer 160 has a multi-layered structure.The intermediate layer 170 is formed over the through hole h and betweenthe selector layer 160 and the metal layer 110, in some embodiments ofthe present disclosure.

FIG. 5(b) shows an alternative embodiment of the embodiment shown inFIG. 5(a). FIG. 5(b) shows a non-symmetrical structure with respect tothe metal layer 110, while FIG. 5(a) shows a symmetrical structure. InFIG. 5(b), the second phase change material layer 130′ is formed overthe second heater 140′, spaced apart from the second selector layer160′. In this embodiment, the second phase change material layer 130′receives heat generated from the top surface of the second heater 140′.If the heat transfer favors an upward direction, the arrangement of thesecond phase change material layer 130′ over the second heater 140′ mayenhance the entire efficiency of the device. In this way, depending onthe heat transfer direction within the memory device, the arrangement ofthe phase change material layers with respect to the heaters can betailored to suit different needs with optimal efficiencies. Theintermediate layer 170 is formed over the through hole h and between theselector layer 160 and the metal layer 110, in some embodiments of thepresent disclosure.

FIGS. 6(a), 6(b), and 6(c) show embodiments having an additionalcomponent, i.e. an intermediate layer 170′. FIG. 6(a) shows that theintermediate layer 170 is formed over the through hole h, between thephase change material layer 130 and the metal layer 110, in someembodiments of the present disclosure. The intermediate layer 170 isformed between the selector layer 160 and the metal layer 110, in someembodiments of the present disclosure.

FIG. 6(a) shows that the second phase change material layer 130′ isformed between the second heater 140′ and the second selector layer160′, in some embodiments of the present disclosure. FIG. 6(b) showsthat the second phase change material layer 130′ is formed over thesecond heater 140′ between the second heater 140′ and the top electrode120′, in some embodiments of the present disclosure. In someembodiments, an additional intermediate layer 170′ is formed on thesecond phase change material layer 130′. FIG. 6(c) shows that anadditional intermediate layer 170′ is formed on the second selectorlayer 160′, a second phase change material layer 130′ is formed over theadditional intermediate layer 170′ and a second heater 140′ is formedover the second phase change material layer 130′, in some embodiments ofthe present disclosure. Depending on the heat transfer direction, FIGS.6(a)-6(c) may enhance the overall efficiency of the PCRAM device.

In FIGS. 6(a), 6(b), and 6(c), the intermediate layers 170 and 170′ areformed of carbon, titanium, titanium nitride, tungsten, andtitanium-tungsten with a thickness of about 1 to 50 nm.

FIGS. 7(a)-7(f), 8(a)-8(i), 9(a)-9(h), and 10(a)-10(g) show the variousmanufacturing operations to make PCRAMs according to the aboveembodiments. It is understood that additional operations can be providedbefore, during, and after processes shown by FIGS. 7(a)-7(f), 8(a)-8(i),9(a)-9(h), and 10(a)-10(g) and some of the operations described belowcan be replaced or eliminated, for additional embodiments of themethods. The order of the operations/processes may be interchangeable.Materials, configurations, dimensions, and/or processes explained withrespect to FIGS. 1(a)-6(c) may be employed in the following embodiments,and the detailed explanation thereof may be omitted.

FIG. 7(a) shows an operation of forming a bottom electrode 120 over asubstrate 100. In some embodiments, the substrate 100 is any substratethat can be used for an electronic memory device, including a singlecrystalline semiconductor material such as, but not limited to, Si, Ge,SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb and InP. Incertain embodiments, the substrate 100 is made of crystalline Si. Insome embodiments, the bottom electrode 120 is formed by evaporation orany vapor deposition method such as CVD, PLD, sputtering, ALD, or anyother thin film deposition method. The bottom electrode 120 can beformed by patterning the formed layer using masking and etchingprocesses such as UV photolithography. To enhance the insulatingproperty between the PCRAM devices or cells, an insulating layer of e.g.silicon oxide is formed (by oxidation or any thin film depositionmethod) over the substrate 100 (not shown) before the bottom electrode120 is formed on the substrate 100.

FIG. 7(b) shows an operation of forming an insulating layer 150 over thebottom electrode 120. The insulating layer 150 is a material selectedfrom the group consisting of silicon oxide (SiO₂), silicon nitride(Si₃N₄), silicon oxynitride (SiON), SiOCN, SiCN, Al₂O₃, fluorine-dopedsilicate glass (FSG), a low-k dielectric material, and other suitabledielectric materials used in manufacturing semiconductor devices. Insome embodiments, the insulating layer 150 is formed, for example, byCVD, such as low pressure chemical vapor deposition LPCVD, plasma-CVD orflowable CVD; PLD; sputtering; ALD; or any other thin film depositionmethod.

FIG. 7(c) shows an operation of forming a patterned photoresist layer200 over the insulating layer 150. FIG. 7(d) shows an operation ofetching the insulating layer 150 using isotropic etching, wet etchingand/or dry etching. The etching forms a through hole h having a width ofabout 10 nm in the insulating layer 150, exposing the bottom electrodelayer 120.

FIG. 7(e) shows an operation of forming a heater 140 in the through holeh. The heater 140 is formed by depositing a metal alloy layer over theinsulating layer 150, followed by a chemical mechanical polishing CMP insome embodiments so that the top surface of the heater 140 is coplanarwith the top surface of the insulating layer 150. The heater 140 formedin FIG. 7(e) is further etched to reduce the thickness in the throughhole h, i.e. forming the embodiments in FIGS. 7(f) and 7(g).

The embodiment in FIG. 7(e) is continued in processing in FIG. 8(a) toform a stacked PCRAM device shown in FIG. 8(i), in some embodiments.FIG. 8(a) shows the embodiment depicted in FIG. 7(e). FIG. 8(b) shows anoperation of forming a patterned phase change material layer 130 overthe heater 140 by one or more thin film deposition and patterningmethods. FIG. 8(c) shows an operation of forming a patterned selectorlayer 160 by one or more thin film deposition and patterning methods.FIG. 8(d) shows an operation of forming an intermediate layer 170 overthe selector layer 160 and forming a metal layer 110 over the selectorlayer 160 by a thin film deposition and patterning method.Alternatively, in other embodiments, the layers 130, 160, 170, and 110are formed together by forming the layers and then patterning the layersin a single step. The intermediate layer 170 is formed over the throughhole h and between the selector layer 160 and the metal layer 110, insome embodiments of the present disclosure. The intermediate layer 170may be formed of carbon, titanium, titanium nitride, tungsten, andtitanium-tungsten with a thickness of about 1 to 50 nm and functions toprevent material diffusion into and contamination of the phase changematerial layer 130. In some embodiments, the intermediate layer 170 isformed by any vapor deposition method such as CVD, PLD, sputtering, ALD,or any other thin film deposition method. In some embodiments, theintermediate layer 170 reduces the incorporation of species from themetal layer 110 into the selector layer 160 and the phase changematerial layer 130. In some embodiments of the present disclosure, thein-plane size of the intermediate layer 170 is greater than thehorizontal cross-sectional size of the through-hole h.

FIG. 8(e) shows an operation of forming and patterning the secondselector layer 160′ and the second phase change material layer 130′ overthe metal layer 110. In some embodiments, the layers 130, 160, 170, 110,160′ and 130′ are patterned by more than one etching processes. FIG.8(f) shows an operation of forming the insulating layer 150′. FIG. 8(g)shows an operation of forming a second through hole h′ by formingphotoresist layer and etching an insulating layer 150″. In someembodiments, the insulating layers 150′ and 150″ are formed as one layerin one operation instead of two layers formed in two separateoperations. Through hole h′ is subsequently formed by etching the oneinsulating layer. In some embodiments, the insulating layers 150, 150′and 150″ are formed of the same materials described above. FIG. 8(h)shows an operation of forming a second heater 140′. FIG. 8(i) shows anoperation of forming a top electrode 120′. In this way, in the formeddevice in FIG. 8(i), the insulating layers 150, 150′, and 150″, togetherwith the top electrode 120′ and the bottom electrode 120, enclose theother components in this device, providing superior electrical andthermal insulating properties and reducing thermal and cross-talkdisturbance.

The embodiment in FIG. 7(f) is continued in processing in FIG. 9(a) toform the embodiment in FIG. 9(h) in some embodiments, and the embodimentin FIG. 7(g) is continued in processing in FIG. 10(a) to form theembodiment in FIG. 10(g) in other embodiments. FIG. 9(a) shows theembodiment depicted in FIG. 7(f). FIG. 9(b) shows an operation offorming a phase change material layer 130 in the through hole h and overthe heater 140 by one or more thin film deposition methods. FIG. 9(c)shows an operation of forming a patterned selector layer 160, anintermediate layer 170, and a metal layer 110 by one or more thin filmdeposition and patterning methods. The intermediate layer 170 is formedover the through hole h and between the selector layer 160 and the metallayer 110, in some embodiments of the present disclosure. Theintermediate layer 170 may be formed of carbon, titanium, titaniumnitride, tungsten, and titanium-tungsten with a thickness of about 1 to50 nm and functions to prevent material diffusion into and contaminationof the phase change material layer 130. In some embodiments, theintermediate layer 170 is formed by any vapor deposition method such asCVD, PLD, sputtering, ALD, or any other thin film deposition method. Insome embodiments, the intermediate layer 170 reduces the incorporationof species from the metal layer 110 into the selector layer 160 and thephase change material layer 130. In some embodiments of the presentdisclosure, the in-plane size of the intermediate layer 170 is greaterthan the horizontal cross-sectional size of the through-hole h.

FIG. 9(d) shows an operation of forming a second selector layer 160′ byone or more thin film deposition and patterning methods. Alternatively,in other embodiments, the three layers 160, 110 and 160′ are formed bythin film deposition methods and then patterned together using apatterning method. FIG. 9(e) shows an operation of forming theinsulating layer 150′. FIG. 9(f) shows an operation of forming a secondthrough hole h′. The second through hole h′ is formed byphotolithography and etching operations in some embodiments. In someembodiments, the insulating layers 150, 150′ and 150″ are formed of thesame material described above. Also, in some embodiments, the insulatinglayers 150′ and 150″ are formed as one layer formed in one operation.FIG. 9(g) shows an operation of forming a second heater 140′ in thesecond through hole h′. FIG. 9(h) shows an operation of forming a topelectrode 120′. In this way, in the formed device in FIG. 9(h), theinsulating layers 150, 150′ and 150″, together with the top electrode120′ and the bottom electrode 120, enclose the other components in thisdevice, thereby providing superior electrical and thermal insulatingproperties and reducing thermal and cross-talk disturbance.

FIG. 10(a) shows the embodiment depicted in FIG. 7(g). FIG. 10(b) showsan operation of forming a first phase change material layer 130 and afirst selector layer 160 in the through hole h and over the heater 140by one or more thin film deposition and patterning methods. FIG. 10(c)shows an operation of forming patterned metal layer 110, an intermediatelayer 170, and patterned second selector layer 160′ by one or more thinfilm deposition and patterning methods. Alternatively, in otherembodiments, the layers 110, 170, and 160′ are formed and then patternedtogether using a patterning method. The intermediate layer 170 is formedover the through hole h and between the selector layer 160 and the metallayer 110, in some embodiments of the present disclosure. Theintermediate layer 170 may be formed of carbon, titanium, titaniumnitride, tungsten, and titanium-tungsten with a thickness of about 1 to50 nm and functions to prevent material diffusion into and contaminationof the phase change material layer 130. In some embodiments, theintermediate layer 170 is formed by any vapor deposition method such asCVD, PLD, sputtering, ALD, or any other thin film deposition method. Insome embodiments, the intermediate layer 170 reduces the incorporationof species from the metal layer 110 into the selector layer 160 and thephase change material layer 130. In some embodiments of the presentdisclosure, the in-plane size of the intermediate layer 170 is greaterthan the horizontal cross-sectional size of the through-hole h.

FIG. 10(d) shows an operation of forming the insulating layer 150′. FIG.10(e) shows another operation of forming a second through hole h′ in theinsulating layer 150″ using photolithography and etching operations insome embodiments. In some embodiments, the insulating layers 150′ and150″ are formed as one layer formed in a single operation. FIG. 10(f)shows an operation of forming a second heater 140′ in the second throughhole h′. FIG. 10(g) shows an operation of forming a top electrode 120′.In some embodiments, the insulating layers 150, 150′ and 150″ are formedof the same materials described above. In this way, in the device inFIG. 10(g), the insulating layers 150, 150′, and 150″, together with thetop electrode 120′ and the bottom electrode 120, enclose the othercomponents in this device, thereby providing superior electrical andthermal insulating properties and reducing thermal and cross-talkdisturbance.

FIG. 11 shows a flowchart of a method of forming an embodiment of thepresent disclosure. The method includes operations S111: forming abottom electrode over a substrate, S112: forming an insulating layerover the bottom electrode, S113: forming a through hole in theinsulating layer, S114: forming a heater in the through hole, S115:forming a phase change material layer over the heater, S116: forming aselector layer over the phase change material layer, S117: forming anintermediate layer over the selector layer, and S118: forming a metallayer over the intermediate layer.

In particular, the operation S115 may include forming the phase changematerial layer over the insulating layer and over the heater, or formingthe phase change material layer in the through hole of the insulatinglayer and over the heater. Also, the operation S116 may include formingthe selector layer over the insulating layer and over the heater orforming the selector layer in the through hole of the insulating layerand over the heater. The process conditions of each operation includethe details of the embodiments disclosed herein. Materials,configurations, dimensions, and/or processes explained with respect toFIGS. 1(a)-1 may be employed in the following embodiments, and thedetailed explanation thereof may be omitted.

FIGS. 12(a), 12(b), 12(c), 12(d), 12(e), and 12(f) show sequentialmanufacturing operations for forming a heater in a through holeaccording to embodiments of the present disclosure. In some embodiments,FIG. 12(a) is consistent with FIG. 7(d) and FIG. 12(f) is consistentwith FIG. 7(e) and FIGS. 12(b), 12(c), 12(d), and 12(e) show sequentialmanufacturing operations for forming heater 140 in the through hole h.As shown in FIGS. 12(b), 12(c), 12(d), and 12(e), a material, e.g., ametal alloy, that forms heater 140 in the through hole h, may bedeposited in more than one step, e.g., in four steps. In each step, onelayer of the material may be deposited in the through hole h, e.g. atthe bottom and sides of the through hole h, and also may be deposited ontop of insulating layer 150. FIGS. 12(b), 12(c), 12(d), and 12(e)respectively correspond to depositing one, two, three, and four layers.In some examples, after depositing four layers, the through hole h maybe filled and the heater 140 may be formed. In some embodiments, in eachstep, a deposition method, e.g., ALD, may be used to deposit 40Angstroms of the material and the sequential depositing of the layersmay continue until the through hole h is filled. In some embodiments,after the through hole h is filled, a CMP may be applied on FIG. 12(e)such that the top surface of the heater 140 becomes coplanar with thetop surface of the insulating layer 150 as shown in FIG. 12(f).

FIGS. 13(a), 13(b), 13(c), and 13(d) show sequential manufacturingoperations for depositing a two-dimensional layer on top of the heaterwhen forming a PCRAM according to embodiments of the present disclosure.Materials, configurations, dimensions, and/or processes explained withrespect to FIGS. 1(a)-12(f) may be employed in the followingembodiments, and the detailed explanation thereof may be omitted.

In some embodiments, FIG. 13(a) is consistent with FIG. 8(d) and FIGS.13(b) and 13(c) show sequential manufacturing operations for forming twodimensional layer 190 on top of heater 140. The two-dimensional layer190 of FIG. 13(b), which may be made of a material such as graphene orMolybdenum disulfide (MoS₂), with a thickness range of about 0.2 nm toabout 2 nm in some embodiments may be deposited on top of heater 140 andon top of insulating layer 150. In other embodiments, the thickness ofthe two dimensional layer 190 is in a range from about 0.5 nm to about 1nm. Then as shown in FIG. 13(c), the two-dimensional layer 190 may bepatterned to have a top surface size to fit the phase change materiallayer 130 that will be deposited on top of the two-dimensional layer190. As shown in FIG. 13(d), other layers that may include selectorlayer 160, intermediate layer 170, and metal layer 110 may be depositedon top of the phase change material layer 130. In some embodiments,after the two dimensional layer 190 is formed as shown in FIG. 13(b),layers for phase change material layer 130, selector layer 160,intermediate layer 170 and metal layer 110 are sequentially formed, andthen by using one or more lithography and etching operations, thestacked layer is patterned to form the structure shown in FIG. 13d ). Insome embodiments, the operation performed in FIGS. 13(b) and 13(c) maybe added between FIGS. 8(a) and 8(b).

FIGS. 14(a), 14(b) and 14(c) show a structure of top and bottomelectrodes that are coupled to a heater. FIG. 14(a) shows heater D2,consistent with heater 140 of FIG. 1(b), that is coupled between topelectrode D1 and bottom electrode D3. Top electrode D1 and bottomelectrode D3 are respectively consistent with metal layer 110 and bottomelectrode 120 of FIG. 1(b). FIG. 14(b) shows a chart of elements thatare includes in top electrode D1, heater D2, and bottom electrode D3along a direction D as shown FIG. 14(a). As shown, top electrode D1includes Ti and N and thus may include titanium nitride (TiN). Bottomelectrode D3 may include copper (Cu) and the heater D2 may include Ta,Si, and N and thus may include tantalum nitride (TiN) in a siliconsubstrate. FIG. 14(c) shows a structure of a memory cell with topelectrode D1, bottom electrode D3, and heater D2 that also includesphase change material layer 130, between D1 and D2, and the memory cellstructure is deposed on substrate 100. In some examples, the memory cellstructure of FIG. 14(c) is used in PCRAM, ReRAM, MRAM, etc. In someembodiments, a two-dimensional layer such as two-dimensional layer 190of FIG. 13(d) is included between D2 and phase change material layer130. In some embodiments, selector layer 160 and/or intermediate layer170 may be included between phase change material layer 130 and D1. Insome examples, a material such as amorphous carbon, with higherresistivity that TiN can be used as heater 140. Amorphous carbon has aresistivity of 3.5E-3 (ohm-cm) which is greater than the resistivity3.0E-4 (ohm-cm) of TiN, although the resistivity of amorphous carbon isless than the resistivity of TaN which is 7.0E-2 (ohm-cm). Amorphouscarbon has a thermal conductivity of 1.1 (W/m-k) which is less than thethermal conductivity 20 (W/m-k) of TiN, and also less than the thermalconductivity of TaN which is 3 (W/m-k).

An embodiment according to the present disclosure includes a memorydevice having a substrate, a bottom electrode disposed over thesubstrate, and an insulating layer disposed over the bottom electrode.The insulating layer has a through hole defined in the insulating layer.A heater is disposed in the through hole. A phase change material layeris disposed over the heater. A selector layer is disposed over the phasechange material layer, an intermediate layer is disposed over thethrough hole, and a metal layer disposed over the selector layer. Insome embodiments, the intermediate layer is wider than the diameter ofthe through hole. In some embodiments, the metal layer is formed to bewider than the phase change material layer. In some embodiments, thephase change material layer is disposed in the through hole. In someembodiments, the selector layer is disposed in the through hole. In someembodiments, an intermediate layer contacts the metal layer. In someembodiments, the intermediate layer is formed of one of carbon andtungsten. In some embodiments, the metal layer functions as a topelectrode.

Another embodiment according to the present disclosure includes a memorydevice having a substrate, a bottom electrode disposed over thesubstrate, and a first heater disposed over the bottom electrode. Afirst phase change material layer is disposed over the first heater. Afirst selector layer is disposed over the first phase change materiallayer. An intermediate layer (170) disposed over the first selectorlayer (160). A metal layer is disposed over the first selector layer. Asecond selector layer disposed over the metal layer. A second heater anda second phase change material layer are disposed over the secondselector layer. A top electrode is disposed over the second heater andthe second phase change material layer, and an insulating layer betweenthe bottom electrode and the top electrode, encloses, with the bottomand top electrodes, the first and second heaters, the first and secondselector layers, the first and second phase change material layers, andthe metal layer. In some embodiments, the metal layer is formed to bewider than the first phase change material layer. In some embodiments,the second heater is disposed over the second phase change materiallayer. In some embodiments, the second phase change material layer isdisposed over the second heater. In some embodiments, the intermediatelayer is wider than the first and second heaters. In some embodiments,an intermediate layer contacts the metal layer. In some embodiments, theintermediate layer is formed of one of carbon and tungsten.

Another embodiment according to the present disclosure is a method ofmanufacturing a memory device. The method includes forming a bottomelectrode over a substrate, forming an insulating layer over the bottomelectrode, and forming a through hole in the insulating layer. A heateris formed in the through hole. A phase change material layer is formedover the heater. A selector layer is formed over the phase changematerial layer. An intermediate layer (170) is formed over the selectorlayer (160), and a metal layer is formed over the selector layer. Insome embodiments, the intermediate layer (170) contacts the metal layer(110). In some embodiments, the phase change material layer is formed inthe through hole. In some embodiments, the intermediate layer is formedof at least one of carbon and tungsten.

The foregoing outlines features of several embodiments or examples sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodiments orexamples introduced herein. Those skilled in the art should also realizethat such equivalent constructions do not depart from the spirit andscope of the present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A memory device comprising: a substrate; a bottomelectrode disposed over the substrate; an insulating layer disposed overthe bottom electrode, the insulating layer having a through hole definedin the insulating layer; a heater disposed in the through hole; a phasechange material layer disposed over the heater; a selector layerdisposed over the phase change material layer; an intermediate layerover the through hole; and a metal layer disposed over the selectorlayer.
 2. The memory device of claim 1, wherein the intermediate layeris wider than a diameter of the through hole.
 3. The memory device ofclaim 1, wherein the metal layer is wider than the phase change materiallayer.
 4. The memory device of claim 1, wherein the phase changematerial layer is disposed in the through hole.
 5. The memory device ofclaim 1, wherein the selector layer is disposed in the through hole. 6.The memory device of claim 1, wherein the intermediate layer contactingthe metal layer.
 7. The memory device of claim 1, wherein theintermediate layer is formed of at least one of carbon and tungsten. 8.The memory device of claim 1, wherein the metal layer functions as a topelectrode.
 9. A memory device comprising: a substrate; a bottomelectrode disposed over the substrate; a first heater disposed over thebottom electrode; a first phase change material layer disposed over thefirst heater; a first selector layer disposed over the first phasechange material layer; an intermediate layer disposed over the firstselector layer; a metal layer disposed over the intermediate layer; asecond selector layer disposed over the metal layer; a second heater anda second phase change material layer disposed over the second selectorlayer; a top electrode disposed over the second heater and the secondphase change material layer; and an insulating layer between the bottomelectrode and the top electrode, enclosing, with the bottom and topelectrodes, the first and second heaters, the first and second selectorlayers, the first and second phase change material layers, and the metallayer.
 10. The memory device of claim 9, wherein the intermediate layerextends wider than the first and second heaters.
 11. The memory deviceof claim 9, wherein the metal layer is wider than the first phase changematerial layer.
 12. The memory device of claim 9, wherein the secondheater is disposed over the second phase change material layer.
 13. Thememory device of claim 9, wherein the second phase change material layeris disposed over the second heater.
 14. The memory device of claim 9,wherein the intermediate layer is wider than the first and secondheaters.
 15. The memory device of claim 9, wherein the intermediatelayer contacts the metal layer.
 16. The memory device of claim 9,wherein the intermediate layer is formed of at least one of carbon andtungsten.
 17. A method of manufacturing a memory device, comprising:forming a bottom electrode over a substrate; forming an insulating layerover the bottom electrode; forming a through hole in the insulatinglayer; forming a heater in the through hole; forming a phase changematerial layer over the heater; forming a selector layer over the phasechange material layer; forming an intermediate layer over the selectorlayer; and forming a metal layer over the intermediate layer.
 18. Themethod of manufacturing the memory device of claim 17, wherein theintermediate layer contacts the metal layer.
 19. The method ofmanufacturing the memory device of claim 17, wherein the phase changematerial layer is formed in the through hole.
 20. The method ofmanufacturing the memory device of claim 17, wherein the intermediatelayer is formed of at least at least one of carbon and tungsten.